1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a warpage-preventive circuit board and method for fabricating the same.
2. Description of Related Art
Semiconductor packaging typically utilizes a substrate as chip carrier for the mounting of one or more semiconductor chips thereon, allowing the mounted semiconductor chips to be externally connected to an external printed circuit board. For instance, BGA (Ball Grid Array) packaging technology is characterized by the use of a substrate as chip carrier whose front side is used for mounting one or more semiconductor chips and whose back side is provided with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package can be mechanically bonded and electrically coupled to an external printed circuit board (PCB) by means of these solder balls.
FIG. 1A is a schematic diagram showing a top view of the layout of traces on a convention BGA substrate 100. As shown, this substrate 100 is predefined with a die-mounting area (as the area enclosed in the dotted box indicated by the reference numeral 110) and formed with a plurality of electrically-conductive traces 120 within the die-mounting area 110. The areas beyond the electrically-conductive traces 120 are a blank area 130 where no electrical components are mounted. Further, a solder mask 140 is formed over the substrate 100 to cover the electrically-conductive traces 120 and the blank area 130 over the substrate 100, which is used in subsequent solder reflow process as mask against solder.
One drawback to the foregoing substrate 100, however, as illustrated in FIG. 1B, is that the electrically-conductive traces 120 are distributed unevenly over the substrate 100, which would make the electrically-conductive traces 120 easily subjected to thermal stresses during high-temperature processes, undesirably causing the substrate 100 to be subjected to warpage. When the substrate 100 warps, it would affect the die-mounting process, or even cause the mounted chip 150 to crack, resulting inequality issue of the finished BGA package.
U.S. Pat. No. 6,380,633 “PATTERN LAYOUT STRUCTRURE IN SUBSTRATE” discloses a solution to the aforementioned problem by providing contiguous dummy circuit regions in the blank area of the substrate
FIG. 2 is a schematic diagram showing a top view of the layout of traces on a BGA substrate 200 which is constructed in accordance with the foregoing US patent. As shown, this substrate 200 is predefined with a die-mounting area 210 and formed with a plurality of electrically-conductive traces 220 within the die-mounting area 210. The blank area beyond the electrically-conductive traces 220 is provided with a contiguous dummy circuit region 230 which is evenly distributed over the substrate 200 so that it can help prevent the electrically-conductive traces 220 to cause the substrate 200 to be subjected to warpage.
One drawback to the foregoing patent, however, is that the dummy circuit region 230 on the substrate 200 is made of copper (Cu) whose CTE (Coefficient of Thermal Expansion) is about 16 ppm□, whereas the substrate 200 is made of bismaleimide trazine (BT) whose CTE is about 14 ppm□; and therefore, in the case of the dummy circuit region 230 being unevenly distributed, the substrate 200 would be nevertheless subjected to warpage due to CTE mismatch between the substrate 200 and the dummy circuit region 230 while undergoing high-temperature processes, such as baking, reflow, and molding.
The foregoing problem of warpage is particularly evident in TFBGA (Thin Finepitch Ball Grid Array) substrate, in which case the warpage could be up to 50 μm to 70 μm that would adversely affect the die-mounting process.